| Article ID | Journal | Published Year | Pages | File Type |
|---|---|---|---|---|
| 10361768 | Pattern Recognition Letters | 2011 | 9 Pages |
Abstract
⺠A Hardware-Software (HW/SW) codesign method for enhanced sensing is addressed. ⺠The SW level aggregates the descriptive and Bayesian regularization paradigms. ⺠The HW level employs a parallelized systolic neural network computing architecture. ⺠Next, the HW/SW codesign is performed adapted to an FPGA processing platform. ⺠Attained near-real time sensing resolution enhancement is validated via simulations.
Related Topics
Physical Sciences and Engineering
Computer Science
Computer Vision and Pattern Recognition
Authors
Y. Shkvarko, A. Castillo Atoche, D. Torres-Roman,