Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
10369526 | Signal Processing | 2005 | 13 Pages |
Abstract
Digital data receivers often operate at a fixed sampling rate 1/Ts that is asynchronous to the baud rate 1/T. A digital equalizer that processes the incoming signal will also operate in the asynchronous clock domain. Existing adaptation techniques for this equalizer involve an error sequence ek that is produced in the synchronous clock domain, and converted to the asynchronous domain via an inverse sampling-rate converter. Several disadvantages of this approach may be avoided by means of an alternative topology that is developed and analyzed in this paper. Numerical results for an idealized optical storage channel serve to illustrate the merits of the approach.
Related Topics
Physical Sciences and Engineering
Computer Science
Signal Processing
Authors
Jan W.M. Bergmans, Maria Yu Lin, David Modrie, Rob Otte,