Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
10411916 | Solid-State Electronics | 2005 | 9 Pages |
Abstract
The architecture, materials choice and process technology for stacked-capacitors in embedded-DRAM applications are a crucial concern for each new technology node. An overview of the evolution of capacitor technology is presented from the early days of planar PIS (poly/insulator/silicon) capacitors to the MIM (metal/insulator/metal) capacitors used for todays 65Â nm technology node. In comparing Ta2O5, HfO2 and Al2O3 as high-k dielectric for use in 65Â nm eDRAM technology, Al2O3 is found to give a good compromise between capacitor performance and manufacturability. The use of atomic layer deposition (ALD) is identified to be an enabling technology for both high-k dielectrics and capacitor electrodes.
Related Topics
Physical Sciences and Engineering
Engineering
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Authors
Eric Gerritsen, Nicolas Emonet, Christian Caillat, Nicolas Jourdan, Marc Piazza, David Fraboulet, Bruce Boeck, Audrey Berthelot, Steven Smith, Pascale Mazoyer,