Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
10706482 | Current Applied Physics | 2005 | 4 Pages |
Abstract
In recent years, power consumption has become one of the most critical design concerns in designing VLSI systems. The reduction of power consumption is inevitably required by the emergence of highly efficient and fast systems, which include CPU (central processor unit), MCU (micro controller unit), cache, et cetera. This paper introduces a new low-power cache controller with successive tag comparison algorithm. Using these methods, the power consumption of a cache can be reduced. Simulation results show that the power consumption of a cache using the proposed method is reduced by 42% compared with conventional methods.
Keywords
Related Topics
Physical Sciences and Engineering
Physics and Astronomy
Condensed Matter Physics
Authors
Tae-Chan Kim, Chulwoo Kim, Bong-Young Chung, Soo-Won Kim,