Novel CMOS multi-bit counter for speed-power optimization in multiplier design

The paper introduces a novel multi-bit counter for efficient binary multiplication. A 7:3 counter is proposed, customized and optimized by 3-pronged approach, firstly by group-wise parallel addition using half-adders, secondly by eliminating redundant carry-generators from the design and finally, by optimizing the resultant hardware. The circuit is designed and optimized on standard static-CMOS. Corner analyses with TT, FF and SS for PVT-variation have been performed on proposed design to study reliability and robustness. A benchmarking exercise on Power-Delay-Product (PDP) with reported candidate designs demonstrates superiority of the proposed design. The study reveals that the 7:3-counter, designed using proposed strategy, has up to 36% less PDP, compared to the best candidate-design. Next, the proposed counters are employed, first to design an 8-b × 8-b Column-Compression (CC) multiplier and thereafter, using decomposition-logic on thus-designed-8-b × 8-b-multipliers, to design a 16-b × 16-b multiplier. The multipliers are optimized on 90-nm standard-CMOS technology and compared for speed-power performance with reported candidate designs at 500 MHz. Simulations show that the presented design of 16-b × 16-b multiplier using proposed 7:3 counter offers 55% less PDP, compared to the best candidate design under identical conditions. Once again, all simulations are performed on TSMC 90-nm CMOS technology at 25 °C temperature and 1.0 V supply-rail.