| Article ID | Journal | Published Year | Pages | File Type |
|---|---|---|---|---|
| 11002517 | AEU - International Journal of Electronics and Communications | 2018 | 44 Pages |
Abstract
A 60â¯GHz low-loss wideband interconnection of a CMOS transmitter and its antenna is presented in this paper. The integrated transmitter consists of an all-digital phase-locked loop (ADPLL) IC chip and a U-slot patch antenna connected through wire bonding and compensation matching circuit to operate in the 57-63â¯GHz frequency band. The system is implemented on a sandwiched printed circuit board (PCB) comprising FR4 to embed the ADPLL and the high-frequency Rogers laminate RO4350B for the antenna and the matching network. The matching circuit is designed in two configurations microstrip and grounded coplanar waveguide (GCPW) to compensate for the wire bond inductance. The capability and sensitivity of these two topologies considering the wire bond geometry variations are compared which points out that GCPW is more robust to wire bonding parasitic effects. Finally, the GCPW matching circuit is fabricated and interconnected to the ADPLL die and its performance is examined using hybrid simulation/measurement data.
Related Topics
Physical Sciences and Engineering
Computer Science
Computer Networks and Communications
Authors
Mahdi Salarpour, Forouhar Farzaneh, Robert Bogdan Staszewski,