Optimization of novel superjunction LDMOS with partial low K layer

In this paper, a novel superjunction LDMOS with partial low K layer (PLK SJ LDMOS) and linear doping region is presented, which not only breaks the silicon limit, but also overcomes the drawback of SOI devices with lower vertical breakdown voltage (BV). In the x direction, the linear doping optimizes the drift region charge distribution and shields the substrate assisted depletion effect (SAD). Finally, the lateral BV of the device is improved. In the y direction, the LK dielectric in the buried layer strengthens the electric field of buried layer, thereby enhancing the vertical withstand voltage. Simulated results show that the PLK SJ LDMOS with the drift region length of 45 μm can achieve BV of 799 V and figure-of-merit (FOM) of 6.2 MW cm−2. Compared with the conventional SJ LDMOS (Con. SJ LDMOS), the BV and FOM are improved by 50% and 72.2%, respectively.