Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
11028119 | AEU - International Journal of Electronics and Communications | 2018 | 24 Pages |
Abstract
In this paper, a new architecture of a fully integrated low-dropout voltage regulator (LDO) is presented. It is composed of hybrid architecture of NMOS/PMOS power transistors to relax stability requirements and enhance the transient response of the system. The LDO is capable of producing a stable output voltage of 1.1â¯V from 1.3â¯V single supply with recovery settling time about 680â¯nsec. It can supply current from 10â¯ÂµA to 100â¯mA consuming quiescent current of 20.5â¯ÂµA and 95â¯ÂµA, respectively. It supports load capacitance from 0 to 50â¯pF with phase margin that increases from 43° at low load (10â¯ÂµA) to 74° at high load (100â¯mA) and power supply rejection ratio (PSRR) less than â20â¯dB up to 100â¯kHz. The proposed LDO is designed in 130â¯nm CMOS technology and occupies an area of 0.11â¯mm2. Post layout simulations show better performance compared with other reported techniques.
Keywords
Related Topics
Physical Sciences and Engineering
Computer Science
Computer Networks and Communications
Authors
Mahmoud H. Kamel, Ahmed N. Mohieldin, El-Sayed Hasaneen, Hesham F.A. Hamed,