Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
11028122 | AEU - International Journal of Electronics and Communications | 2018 | 21 Pages |
Abstract
This paper introduces a 9-bit time-based capacitance-to-digital converter (T-CDC). This T-CDC adopts a new design methodology for parasitic cancellation with a simple calibration technique. In T-CDCs, the input sensor capacitance is first converted into a delay pulse using a capacitance-to-time converter (CTC) circuit; then this delay signal is converted into a digital code through a time-to-digital converter (TDC) circuit. A prototype of the proposed T-CDC is implemented in UMC 0.13â¯Î¼m CMOS technology. This T-CDC consumes 8.42â¯Î¼W and achieves a maximum SNR of 45.14â¯dB with a conversion time of 1â¯Î¼s that corresponds to a figure of merit (FoM) of 16.4â¯fJ/Conv.
Keywords
Related Topics
Physical Sciences and Engineering
Computer Science
Computer Networks and Communications
Authors
Ali H. Hassan, Ahmed Fouad, Hassan Mostafa, Khaled N. Salama, Ahmed M. Soliman,