A simplified radix-4 successive cancellation decoder with partial sum lookahead

Polar codes recently received high attention by researchers as proven to approach channel capacity at higher codeword length. However, the decoding latency grows significantly with codeword length, rendering implementation for latency constrained applications impossible. To tackle this problem, this paper proposes a polar decoder architecture based on radix-4 processing units with a special last stage processing unit to decode up to 16 bits in the same clock. In addition, it proposes decoding extended special subcodes to reduce latency. Moreover, it uses partial sum look-ahead technique, resulting in a high throughput low latency decoding architecture.