Article ID Journal Published Year Pages File Type
1552496 Superlattices and Microstructures 2016 15 Pages PDF
Abstract

•Low power performance of nanoscale junctionless (JL) MOSFETs is optimized.•Impact of channel doping, underlap spacer, etc. on performance metrics is studied.•ON-current for a fixed OFF-current, subthreshold swing & delay are optimized.•Our proposed JL MOSFETs outperform Si FinFETs at channel length of 34 nm.

Ultra-low power logic applications at advanced CMOS technology nodes have been extensively investigated nowadays to increase packing density in Integrated Circuits at a lower cost. Junctionless (JL) transistors have emerged as promising alternatives to conventional MOSFETs because of their relatively easy fabrication steps and extreme scalability. We perform a detailed numerical study to evaluate the effects of channel doping concentration, dielectric constant of underlap spacers, source/drain resistance on logic performance of 20 nm gate length JL MOSFETs in terms of ON-current at a given OFF-current, subthreshold swing, gate capacitance and intrinsic delay for supply voltages ranging 0.4–0.75 V. In comparison with the reported experimental data for inversion-mode device, our optimized JL device exhibits enhancement of ION by 15.6%, reduction of drain-induced barrier lowering (DIBL) by 22.5% while preserving equally low SS of 61.5 mV/decade at channel length of 34 nm and supply voltage of 0.75 V.

Related Topics
Physical Sciences and Engineering Materials Science Electronic, Optical and Magnetic Materials
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