Implementation of carbon nanotube bundles in sub-5 micron diameter through-silicon-via structures for three-dimensionally stacked integrated circuits

Carbon nanotubes (CNT) are being intensely investigated and explored as an alternative to the use of traditional metals in the interconnects for 3D chip-stacking, because of its numerous advantageous properties, in particular high thermal and electrical conductivity that are several times higher than of any comparable metal. In this work, we have successfully implemented growth and realized functional integration of multiwalled-CNT bundles in sub-5 μm diameter, high-aspect ratio ‘Through-Silicon-Vias’ (TSV). Large-area growth of CNT bundles was realized in TSVs on top of metal-lines in a bottom-up approach, at complimentary-metal-oxide-semiconductor processing-compatible temperatures. An innovative approach for minimization of the interfacial-barrier contact resistance between CNT and metal-lines was adopted, by introducing an alloy of Al-rich Al2O3 as catalyst-holding layer, instead of conventional 10 nm. Good electrical-contact between metal-lines to CNTs is observed. A repeatable, non-destructive approach was used for electrical characterization studies of CNT-TSVs. The combined electrical resistance of an individual CNT-filled TSV was found to be ∼1.2 kΩ. Issues related to selective deposition of Fe-catalyst thin-film at the TSV-bottom, and growth of the CNTs from TSV sidewalls were solved by novel approach of wafer-to-wafer bonding. Structural investigations proved that as-grown CNT bundles are anchored robustly in the metal-layers.