A Novel Architecture for Scan Cell in Low Power Test Circuitry

Over the past decade VLSI manufacturing industry flourishing very rapidly. Now a days hundreds and thousands of millions of transistors that are incorporated on a chip. As the circuit complexity increasing design for test circuitry also became more complex. These complex test circuitry heavily stressed to check the functionality of the CUT (Circuit under Test). Compared with normal functional mode, Power dissipation during test mode is much higher. Power dissipation during testing is more than twice compared with normal functional mode. Large Test data volume and High power consumption are the main problems in Design for Testability. This excessive power consumption is mainly due to switching of the scan cells. The technique proposed in this paper reduces switching activity in the scan cells there by the power consumption during testing can be reduced. In the proposed scan cell architecture some of the idle flip-flops are disabled during scanning using a control signal. By disabling idle flip-flops can be possible by an external control signal or with any internal signal. Excessive power consumption during testing may cause performance degradation and high system cost. These problems can be eliminated with the proposed scan cell architecture.