Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
396143 | Information Sciences | 2007 | 12 Pages |
Abstract
A graph model for describing the relationships among wire segments is crucial to constrained via minimization (CVM) in a VLSI design. In this paper we present a new graph model, called the conjugate conflict continuation graph, for multi-layer CVM with stacked vias. This graph model eases the handling of stacked via problems. An integer linear programming (ILP) formulation and a simulated annealing (SA) algorithm based on this graph model are developed to solve multi-layer CVM. The ILP model is too complicated to solve efficiently. The SA algorithm on average achieves 6.4% via reduction for layouts obtained using a commercial tool under a set of practical constraints in which the metal wires (including pins) used in cell layouts, power rails and rings, and clock routing are treated as obstacles or fixed-layer objects to a multi-layer CVM.
Related Topics
Physical Sciences and Engineering
Computer Science
Artificial Intelligence
Authors
Rung-Bin Lin, Shu-Yu Chen,