On design and implementation of three phase three level shunt active power filter for harmonic reduction using synchronous reference frame theory

•SRF theory is implemented to extract the reference current signals for 3-level SAPF.•The SRF algorithm has been implemented using Xilinx XC3SD1800A – FG676-4 Spartan 3A DSP FPGA processor. It can be concluded that a THD obtained as low as 2.0% which is well below the existing results 5.0%.•The experimental results and simulated results prove that the Total Harmonic Distortion (THD), reactive power and power factor of three phase three level SAPF are found to be quite satisfactory with unbalanced and non-linear loads and it complies with the IEEE standards.

Shunt active power filter is commonly used to eliminate current harmonics generated in the source side due to presence of non-linear loads. This scheme consists of three phase three level diode clamped multilevel inverter and a DC capacitor that act as a shunt active power filter to mitigate the supply current harmonics and inject the required reactive power to non-linear loads. In this paper, using synchronous reference frame algorithm, a three phase three level SAPF is implemented on an embedded platform. In SRF theory, reference signals are transformed from a–b–c stationary frame to 0–d–q rotating frame. The reference signals in the 0–d–q rotating frame are controlled to get the desired reference signals using PI controller. The PWM signal generation for the three phase three level inverter is computed directly from the sampled amplitudes of the reference phase voltages. The practical implementation of the SAPF is realized using Xilinx XC3SD1800A – FG676-4 Spartan 3A DSP FPGA controller. This system is simulated using MATLAB/SIMULINK and the simulation results are compared with prototype hardware model for validating the effectiveness of the proposed system. Based on the studies, it is concluded that the SAPF is easy for implementation for reducing the Total Harmonic Distortion below 5% as per IEEE-519 standard.