Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
405678 | Neurocomputing | 2016 | 13 Pages |
Abstract
In this paper, we propose the architecture of a fault-tolerant unit in a modular neurocomputer that is based on decoding with computation of errors syndromes on redundant moduli and implemented using FPGA and a finite ring neural network. The computational complexity of the proposed architecture is about 80% less in comparison with that of the architecture based on number projections in the mixed radix number system.
Related Topics
Physical Sciences and Engineering
Computer Science
Artificial Intelligence
Authors
N.I. Chervyakov, P.A. Lyakhov, M.G. Babenko, A.I. Garyanina, I.N. Lavrinenko, A.V. Lavrinenko, M.A. Deryabin,