Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
406490 | Neural Networks | 2013 | 23 Pages |
Abstract
We present a design framework for neuromorphic architectures in the nano-CMOS era. Our approach to the design of spiking neurons and STDP learning circuits relies on parallel computational structures where neurons are abstracted as digital arithmetic logic units and communication processors. Using this approach, we have developed arrays of silicon neurons that scale to millions of neurons in a single state-of-the-art Field Programmable Gate Array (FPGA). We demonstrate the validity of the design methodology through the implementation of cortical development in a circuit of spiking neurons, STDP synapses, and neural architecture optimization.
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Physical Sciences and Engineering
Computer Science
Artificial Intelligence
Authors
Andrew S. Cassidy, Julius Georgiou, Andreas G. Andreou,