Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
422251 | Electronic Notes in Theoretical Computer Science | 2008 | 14 Pages |
Abstract
The broad availability of multi-core chips on standard desktop PCs provides strong motivation for the development of new algorithms for logic model checkers that can take advantage of the additional processing power. With a steady increase in the number of available processing cores, we would like the performance of a model checker to increase as well – ideally linearly. The new trend implies a change of focus away from cluster computers towards shared memory systems. In this paper we discuss the multi-core algorithms that are in development for the SPIN model checker.
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