| Article ID | Journal | Published Year | Pages | File Type |
|---|---|---|---|---|
| 423170 | Electronic Notes in Theoretical Computer Science | 2006 | 11 Pages |
Abstract
We describe the application ESBC to perform the timing analysis of a combinatorial circuit. The circuit is described by formulas of Classical Logic and the delays of propagation of the signals in a gate are represented by a kind of valuation form semantics. ESBC computes the exact stabilization times at which the output signals stabilize.
Related Topics
Physical Sciences and Engineering
Computer Science
Computational Theory and Mathematics
