Multi-Clock Latency-Insensitive Architecture and Wrapper Synthesis 1

This paper presents an architecture and a wrapper synthesis approach for the design of multi-clock systems-on-chips. We build upon the initial work on multi-clock latency-insensitive systems by Singh and Theobald [Montek Singh and Michael Theobald. Generalized latency-insensitive systems for single-clock and multi-clock architectures. In Proc. Design, Automation and Test in Europe (DATE), February 2004], and provide a detailed system architecture with the following capabilities and benefits: (i) modules are stalled only when needed, thereby avoiding unnecessary stalling, (ii) adequate metastability resolution is provided, (iii) handshake interfaces between modules are high-performance and low-latency, i.e., capable of transfering data packets on every clock cycle, (iv) IP cores with large clock distribution delays are correctly handled, and (v) an automated approach is provided for wrapper synthesis from formal specifications. For wrapper synthesis, we chose the Component Wrapper Language (CWL) from Hitachi/Fujitsu [Fujitsu Ltd., Fujitsu Laboratories Ltd., and Hitachi Ltd. Component wrapper language. http://www.labs.fujitsu.com/en/techinfo/cwl/index.htm] as the specification language. Our synthesis approach has been implemented in a prototype tool. Synthesis results for a small set of examples are provided.