GALS Test Chip on 130nm Process

We present a Globally Asynchronous Locally Synchronous test chip fabricated on a 130nm silicon process. The primary design goals of this chip were to measure the stability of local clocks on a deep submicron process technology, evaluate difficulties using GALS in a standard design flow, and to measure power consumption. The original Asynchronous Wrapper building blocks were used to construct a configurable data pipeline that can be tuned to emulate the operation of many different types of algorithms.