Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
425050 | Future Generation Computer Systems | 2006 | 7 Pages |
Abstract
A single-chip shared-memory multiprocessor architecture is introduced which is particularly well suited to common bioinformatic computing tasks. The architecture uses asynchronous bus interfaces to create an integrated circuit design methodology allowing for scaling of the multiprocessor with very little design effort. A key aspect of this design methodology is that it is not necessary to expend significant design resources and chip area on the clock tree. An analysis of the Smith–Waterman alignment algorithm running on this architecture shows that the performance penalty due to increased bus latency compared to a fully synchronous architecture is negligible
Keywords
Related Topics
Physical Sciences and Engineering
Computer Science
Computational Theory and Mathematics
Authors
Scott F. Smith, James F. Frenzel,