| Article ID | Journal | Published Year | Pages | File Type |
|---|---|---|---|---|
| 427343 | Information Processing Letters | 2011 | 5 Pages |
In this letter, we present a speedup of bit-parallel Karatsuba multiplier in GF(m2)GF(2m) generated with a class of irreducible trinomials. Applying a slightly modified Karatsuba approach, we can save one XOR gate delay at the cost of little increase of space complexity. The proposed multiplier has a lower time complexity than the previous Karatsuba multipliers except for those based on equal-space trinomial or all-one polynomial. In counterpart it only requires one more XOR time delay than the best known multipliers for trinomials but maintains a smaller number of logic gates.
Research highlights► We derive a modification of classic Karatsuba approach which can simplify polynomial reduction. ► Modified Karatsuba approach enables a speedup for bit-parallel Karatsuba based multiplier generated with trinomial. ► New multiplier proposed a trade-off between space and time complexity.
