Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
439148 | Theoretical Computer Science | 2008 | 15 Pages |
Abstract
In this article, a verification methodology for mixed-signal circuits is presented that can easily be integrated into industrial design flows. The proposed verification methodology is based on formal verification methods. A VHDL behavioral description of a mixed-signal circuit is transformed into a discrete model and then verified using well-established tools from formal digital verification. Using the presented methodology, a much higher coverage of the functionality of a mixed-signal circuit can be achieved than with simulation based verification methods. The approach has already been successfully applied to industrial mixed-signal circuits.
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