Area-efficient pixel rasterization and texture coordinate interpolation

In this paper, new pixel rasterization and texture coordinate interpolation algorithms are presented to reduce silicon area. The proposed pixel rasterization based on the characteristics of edge function saves silicon area in terms of gate count by 38.9% and 35.3% compared to the previous centerline and scanline algorithms, respectively. The proposed texture coordinate interpolation combines the benefits of division and midpoint iteration in order to reduce silicon area without performance loss in computing the fraction part of texture coordinates, which is required for texture filtering. The proposed texture coordinate interpolation architecture uses less silicon gates than the architecture using dividers, and the gate count reduction ratios are 25.2% and 37.0% for 16- and 32-bit texture coordinates, respectively. The hardware feasibility of the proposed architecture is proved by implementation into a three-dimensional (3D) graphics SoC.