A new passive sample and hold structure for high-speed, high-resolution ADCs

A new wideband, high linear passive sample and hold (S/H) structure is presented. Reducing the sampling switch voltage dependency on input signal is the key idea to linearize conventional S/H structure. The sampling switch is immunized from signal dependent charge injection and signal feedthrough by using cross coupling technique in fully differential topology. Furthermore, the proposed structure enables the merge of offset cancellation cycle for S/H subsequent stage with the sampling cycle, simultaneously. The simulation results for the designed 12-bit, 500 Msps S/H in standard 0.18 μm CMOS process with 700 MHz input bandwidth, show 12 dB and 7.2 dB improvement on THD and signal feedthrough, respectively. These values are 14 dB and 10 dB for similar 12bit 250 Msps 500 MHz input bandwidth S/H circuits designed in standard 0.35 μm CMOS process.