Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
446704 | AEU - International Journal of Electronics and Communications | 2009 | 6 Pages |
Abstract
In this paper, a method to reduce the errors generated by the second order effects in the current-mode circuits employing MOS translinear loop is proposed. Using this method a square-root circuit, a squarer/divider circuit and a multiplier/divider circuit are designed and presented. They are suitable for standard CMOS fabrication and analog systems.
Related Topics
Physical Sciences and Engineering
Computer Science
Computer Networks and Communications
Authors
S. Menekay, Rıza Can Tarcan, Hakan Kuntman,