Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
447283 | AEU - International Journal of Electronics and Communications | 2016 | 9 Pages |
Abstract
A low-power high-speed two-stage dynamic comparator is presented. In this circuit, the voltage swing of the first stage of the comparator, pre-amplifier stage, is limited to Vdd/2 in order to reduce the first stage power consumption. Also, this voltage swing limitation provides a strong drive at the evaluation phase for the second stage to enhance the comparison speed. Analytical derivations along with post layout simulation results prove that the proposed method speeds up the conventional circuit by a factor of two in the same budget of power consumption and offset voltage. Furthermore, the proposed circuit offers a wide input common mode range as large as the supply voltage while employing PMOS transistors at the input of the comparator.
Keywords
Related Topics
Physical Sciences and Engineering
Computer Science
Computer Networks and Communications
Authors
Ata Khorami, Mohammad Sharifkhani,