Optimization of a fractional-N frequency synthesizer for UMTS application with a VHDL-AMS description

In this study, we expose new approaches to design and optimize systems at a high level description using Very High Speed Integrated Circuit Hardware Description Language for Analog and Mixed Systems (VHDL-AMS) standard. We detail a theoretical approach to develop self-tuned VHDL-AMS models and we expose some simulations obtained after the optimization of a fractional-NN frequency synthesizer's performances used for wireless systems. The applied optimization method uses the “experience plans” with seven generics having in view to minimize the loop response time and the synthesizer output frequency.