A 16 Hz–160 kHz memristor emulator circuit

This paper reports experimental tests of a memristor emulator circuit employing a double output second generation current conveyor, a four quadrant analog multiplier, a capacitor and two resistors. First, the behavioral model of the proposed emulator circuit is derived, including parasitic elements and exhibiting that the memristance of a charge-controlled memristor is modeled as a first-order function. Subsequently, an analysis on the frequency performance is done, showing not only that the frequency-dependent pinched hysteresis loop in the current-versus-voltage plane holds up to 160 kHz, but a guideline for choosing the numerical values of the passive elements according to the desired operating frequency is also given. Afterwards, the emulator circuit is built with commercially available devices, confirming good agreement among theoretical simulations, HSPICE results and experimental tests. Furthermore, we show that by using a simple switch, the emulator circuit can be configured as decremental or incremental memristor in order to be used in future applications such as sensors, cellular neural networks, chaotic systems, programmable analog circuits and nonvolatile memory devices.