Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
449512 | AEU - International Journal of Electronics and Communications | 2008 | 9 Pages |
Abstract
A new open-loop high-speed CMOS sample-and-hold is presented. Based on new method for further reduction of voltage-dependent charge injection, a new CMOS sample-and-hold was designed. Simulation results confirm the effectiveness of this method. Over 10 dB improvement in signal-to-noise ratio, compared to the signal-to-noise ratio of conventional bottom plate sampling S/Hs was achieved with this method. A comparison between newly designed S/H and the bottom-plate sampling S/H is presented.
Keywords
Related Topics
Physical Sciences and Engineering
Computer Science
Computer Networks and Communications
Authors
Morteza Mousazadeh, Khayrollah Hadidi, Abdollah Khoei,