Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
453889 | Computers & Electrical Engineering | 2007 | 15 Pages |
Abstract
In this paper two different approaches to the design of a reconfigurable Tate pairing hardware accelerator are presented. The first uses macro components based on a large, fixed number of underlying Galois Field arithmetic units in parallel to minimise the computation time. The second is an area efficient approach based on a small, variable number of underlying components. Both architectures are prototyped on an FPGA. Timing results for each architecture with various different design parameters are presented.
Related Topics
Physical Sciences and Engineering
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Authors
Maurice Keller, Robert Ronan, William Marnane, Colin Murphy,