Combined heuristics for synthesis of SOCs with time and power constraints

This paper looks at the highest design level and presents a methodology for designing Systems On Chip (SOC) with low energy dissipation. The aim is achieved through a functional decomposition of the system, followed by an appropriate allocation of tasks to the different components of the system (ASICs and processors). With our approach, it is possible to generate architectures with different features (time and energy), which allows the designer to fastly obtain the architecture that best suits his application.

Graphical abstractFigure optionsDownload full-size imageDownload as PowerPoint slideHighlights► Functional partitioning. ► Allocation of tasks to the system components (processors, ASICs). ► System synthesis subject to time and energy constraints. ► Use of efficient and combined heuristics to deal with intractable problems.