Improved CMOS (4; 2) compressor designs for parallel multipliers

We propose three new (4; 2) compressors via improving best previous designs by replacing an integral portion of relevant logical circuits by an optimized CMOS full-adder. Two other new (4; 2) compressors are also proposed based on new interpretation of logical equations that describe the corresponding functionality. The key design point is to use an available signal, in the sum path, for carry generation. All the proposed and referenced designs are evaluated by exhaustive HSPICE simulations at various temperatures, voltage scaling situations, load capacitances, and presence of process variation using the post-layout CMOS library of standard cell. These experiences show performance improvements, compared to the best of reference designs, in terms of delay (5%), power (16%), and PDP (26%), respectively. To evaluate the studied and new (4; 2) compressors in a more practical environment, we utilized them for implementation of 54 × 54-bit parallel multipliers. Experimental results via MAGMA design tools confirmed the results that we achieved for isolated single (4; 2) compressors.