Improvements on the design and implementation of DVB-S2 LDPC decoders

The architecture of a field-programmable gate-array (FPGA) implementation of a low-density parity-check (LDPC) decoder for the Digital Video Broadcasting – Second Generation via Satellite (DVB-S2) standard is presented. Algorithms are devised to systematically apply the values given in DVB-S2 to implement a memory mapping scheme, which allows for 360 functional units (FUs) to be used in decoding and supports both normal and short frames. A design of a parity-check module (PCM) is presented that verifies the parity-check equations of the LDPC codes. Furthermore, a special characteristic of five of the codes defined in DVB-S2 and their influence on the decoder design is discussed.Two versions of the LDPC decoder are synthesized for two families of FPGAs. The results show that the decoder presented uses fewer hardware resources than a DVB-S2 LDPC decoder found in the current literature that also uses FPGA, while improving the maximum frequency of the decoder.

Graphical abstractFigure optionsDownload full-size imageDownload as PowerPoint slideHighlights► Memory mapping algorithm for LDPC decoders compliant with DVB-S2 has been devised. ► Architecture of parity-check module, which is not clear in literature, is presented. ► Special short frame code rates in DVB-S2 are identified and workaround is proposed. ► Decoder architecture in this paper reduces FPGA hardware resource utilization.