Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
454157 | Computers & Electrical Engineering | 2010 | 10 Pages |
In an attempt to improve the speed of VLSI signal processing systems, a new architecture for a high-speed multiply–accumulate (MAC) unit optimized for digital filters is proposed. This unit is designed as a coprocessor for the LEON2 RISC processor [LEON2 Processor; 2005 [Online].