Design and VLSI implementation of a high-performance face detection engine

This paper proposes a novel hardware structure and field-programmable gate array (FPGA) implementation method for real-time detection of multiple human faces with robustness against illumination variations. These are designed to greatly improve face detection in various environments with using MCT techniques and the AdaBoost learning algorithm which is robust against variable illumination. We have designed, implemented, and verified the hardware architecture of the face detection engine for high-performance face detection and real-time processing. The face detection chip is developed by verifying and implementing it using a FPGA and an application-specific integrated circuit (ASIC). To verify and implement the chip, we used a Virtex5 LX330 FPGA board and a 0.18 μm 1-poly and 6-metal CMOS logic process. Performance results of the implementation and verification showed it is possible to detect at least 32 faces of a wide variety of sizes at a maximum speed of 147 frames per second.

Graphical abstractProposed block diagram of face detection engine.Figure optionsDownload full-size imageDownload as PowerPoint slideHighlights► A novel hardware structure is proposed for real-time face detection. ► FPGA and VLSI implementation of a high-performance face detection engine. ► The Adaboost learning and MCT to enable robust against variable illumination. ► The proposed architecture greatly improves face detection in various environments.