| Article ID | Journal | Published Year | Pages | File Type |
|---|---|---|---|---|
| 455371 | Computers & Electrical Engineering | 2009 | 5 Pages |
Abstract
A hardware architecture for GF(2m) multiplication and its evaluation in a hardware architecture for elliptic curve scalar multiplication is presented. The architecture is a parameterizable digit-serial implementation for any field order m. Area/performance trade-off results of the hardware implementation of the multiplier in an FPGA are presented and discussed.
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Authors
Miguel Morales-Sandoval, Claudia Feregrino-Uribe, René Cumplido, Ignacio Algredo-Badillo,