| Article ID | Journal | Published Year | Pages | File Type |
|---|---|---|---|---|
| 455670 | Computers & Electrical Engineering | 2013 | 8 Pages |
•The maximum clock is about 200 MHz.•The capacitance of W-bus and all modules are small.•The power consumption and latency are all small.
This paper provides an arithmetic controller comprising: an arithmetic logic unit having a plurality of arithmetic instructions, such as ADD (Addition), SUB (Subtraction), MUL (Multiplication), and DIV (Division) instructions. This arithmetic processor was implemented by a cell-based flow and supports the basic mathematical operations, and numerical control.All mathematical instructions are composed of three bytes. In the first byte, it contains the operation code and the address of the operand, while the operands are in the second and third bytes. While the processor architecture compared with the conventional CPU, the performance is speed up for the number reduction of instruction cycle. The number of instruction cycle is decreased to five T-states. All of these circuits were implemented by the TSMC 0.35 μm cell library. A 20-pin I/O PAD was selected to package this processor. The experimental results are showed and discussions are made.
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