Systolic parallel architecture for brute-force autoregressive signal modeling

•We propose a parallel architecture in the form of a systolic automaton for autoregressive (AR) modeling.•We systolically implement the brute-force minimum mean square solution of AR modeling rather than the iterative recursive least squares (RLS) solution.•Throughput and latency are improved compared to existing systolic RLS solutions of AR modeling.•The only disadvantage is the inaccuracy in computing the autocorrelation function (ACF) values for large lags, which can best be remedied by appropriately scaling the ACF.

The paper describes a parallel architecture in the form of a systolic automaton consisting of three distinct stages for the computation of the model parameters of an autoregressive (AR) signal. The three stages perform auto-correlation, matrix triangularization, and backward substitution; they are designed such that their combination computes the brute-force Wiener-Hopf solution to this minimum-mean-square problem in a completely parallel fashion. The signal values are fed serially into the array of the first stage, and the AR parameters emerge from the array cells of the last stage, one parameter from each. Although the systolic architecture under consideration aims at computing the AR parameters that minimize the mean square error (MSE) rather than the least squares sum, thereby limiting its use to time-invariant environments, it has the potential for improved throughput and reduced latency compared to existing methods.

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