Hardware implementation of the elitist compact Genetic Algorithm using Cellular Automata pseudo-random number generator

•We implemented in hardware, two kinds of compact Genetic Algorithms.•We implemented in hardware, two different pseudo-random generators.•The above systems were evaluated using five different test functions.•A detail explanation and a compared evaluation of the designs are presented.

In this paper the design and implementation of two versions of the compact Genetic Algorithm (cGA), with and without mutation and elitism, and a Cellular Automata-based pseudo-random number generator on a Field Programmable Gate Arrays (FPGAs) are accomplished. The design is made using a Hardware Description Language, called VHDL. Accordingly, the obtained results show that it is viable to have this searching algorithm in hardware to be used in real time applications.

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