Design and implementation of a two-dimensional sound field solver based on the Digital Huygens’ Model

•A parallel systolic architecture to exploit both the spatial and temporal parallelism of computation.•Presentation of system architecture, design, and implementation.•Evaluation and analysis of calculation time, data transfer speed, and data throughput in the proposed solver.

Sound field analysis is complicated and computationally intensive. In this paper, a two-dimensional sound field solver based on the Digital Huygens’ Model (DHM) is designed and implemented by a Field Programmable Gate Array (FPGA). In this sound field solver, the original DHM and its boundary condition are extended to reduce operations and hardware resource consumption. The computation is completed locally, and external memory access is avoided. In a two-dimensional space with both length and width being 1.28 m, when boundaries are rigid walls, the FPGA-based analysis system enhances performance from 44 to 217 times, and from 37 to 179 times against the software simulations based on the original DHM and Standard Leapfrog Finite-difference Time-domain (SLF-FDTD), respectively. Compared with the General-purpose Graphic Processing Unit (GPGPU) Tesla C1060, it speeds up by 1223 times in computation and by 114 times in overall performance in the case of time steps being 20,000. When the node scales are different and the calculated time steps are 32,000, the FPGA-based sound field solver achieves about 1795 and 1190 times faster in computation, 218 and 179 times enhancement in final performance over the software simulations based on the original DHM and SLF-FDTD, respectively. Furthermore, the proposed system provides high data throughput, and is easily applied in real-time applications.