A wire delay-tolerant reconfigurable unit for a clustered programmable-reconfigurable processor

Wire delay is rapidly becoming a major bottleneck in reconfigurable systems, creating a significant gap between the clock rates of reconfigurable logic and custom circuits. In this paper, we describe the design of the reconfigurable clusters on the Amalgam clustered programmable-reconfigurable processor. Amalgam’s reconfigurable clusters are divided into four segments of reconfigurable logic, limiting the length of individual wires in the cluster. They support pipelining of wire delays by providing pipeline registers at the intersections between wires in the reconfigurable cluster, retiming buffers at the inputs and outputs of logic blocks, and register queues that reduce the amount of inter-cluster synchronization required in programs. Together, these mechanisms increase the clock rates of Amalgam’s reconfigurable clusters by up to 70%, allowing Amalgam to maintain a 2.6× performance advantage over a purely-programmable processor in a wide range of fabrication processes.