Efficient architecture of adaptive rood pattern search technique for fast motion estimation

This paper presents efficient VLSI architecture for fast Motion Estimation (ME) using Adaptive Rood Pattern Search (ARPS) technique. The proposed architecture uses a single processing element (PE) and simplified memory addressing to reduce the hardware complexity. The addressing logic, which is presently applied to 352 × 288 CIF frames, can be easily extended to frames of higher resolutions. The proposed architecture uses optimum area while satisfying speed requirements for real-time video processing. Implemented in Verilog HDL and mapped to Virtex 6 (XC6VLX75T-3) FPGA, the architecture uses only 165 slice registers and 273 slice LUTs. The architecture can process 240 frames per second while operating at a maximum frequency of 320 MHz.