Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
461705 | Microprocessors and Microsystems | 2009 | 7 Pages |
Abstract
Variable block size (VBS) motion compensated prediction (MCP) provides substantial rate-distortion performance gain over conventional fixed-block-size MCP and is a key feature of the H.264/AVC video coding standard. VBS-MCP requires the encoder to perform VBS motion estimation (VBSME), a computationally complex operation. In this paper, we propose a high motion vector throughput full-search VBSME architecture. High performance is achieved by performing parallel computations for multiple pixels within a macroblock, as well as computing several candidate motion vector (MV) positions in parallel. Two implementations of the architecture are examined, a four pixel-parallel implementation, and a higher performance 16 pixel-parallel implementation. A high degree of scalability is achieved by allowing for a variable length processing element array, where more processing elements yields a higher degree of candidate MV parallelism. The proposed architecture achieves a throughput exceeding current full-search VBSME architectures.
Related Topics
Physical Sciences and Engineering
Computer Science
Computer Networks and Communications
Authors
Stephen Warrington, Wai-Yip Chan, Subramania Sudharsanan,