Multi-lane architecture for eigenface based real-time face recognition

The concept of simultaneously processing different non-overlapping spatial regions of an image and combining the results to obtain a final image is used in this paper. We apply this concept to the domain of face recognition using Principal Component Analysis (PCA). We have shown in [1] that modular PCA improves the accuracy of face recognition when the face images have varying expression and illumination. In this work we design and implement the modular PCA algorithm for face recognition in a Field Programmable Gate Array (FPGA) environment. Since modular PCA processes non-overlapping regions of a face image to produce weight vectors, we design a parallel architecture where each parallel path has a processing element to process a predefined region of a face image. Each processing element computes a weight vector from a face image region and pre-computed eigenvectors; hence the processing element is also parallelized where each path works on one eigenvector and the face image region to compute one element in the weight vector. Each of these paths is pipelined to process the pixels from the face image region and corresponding elements from the eigenvectors in a faster manner. We name this design having pipelined parallel paths as multi-lane architecture. The architecture is able to recognize a face image from a database of 1000 face images in 11 ms.