Statically adaptive multi FIFO buffer architecture for network on chip

In this paper, we present the architecture of a simple input-port that utilizes a static but adaptive Virtual Channel (VC) mechanism. In our approach, the flits of one packet can interleave with the other flits of different packets in a channel and a single buffer by using a rotating flit-by-flit arbitration. The routing path of each flit can be guaranteed because the flits belonging to a packet are attached with an ID tag at each router. Then these flits become differentiable at downstream routers. These tagged interleaved flit-by-flit flow of packet can be controlled and stored in a single memory buffer at different specific area called VC. We further develop the control part of single memory to give an adaptive property to the VCs of a channel. Our approach prevents the monopoly of channel’s buffer by a VC because of the static nature of VCs. Moreover, the adaptive nature of our approach lets the VCs allocate different size of buffers according to traffic demand. Overall, our Statically Adaptive Multi FIFO (SAMF) approach improves the NoC performance metrics such as throughput, latency and buffer utilization by employing an efficient hardware overhead as compared to a conventional static VC mechanism.