Minimizing power loss in optical networks-on-chip through application-specific mapping

The next generation of Multiprocessor Systems-on-Chip will require communication facilities that cannot be provided by traditional electronic communication infrastructures. Silicon photonics appears today a promising solution to handle future communication needs thanks to ultra-high bandwidth and extremely low-power consumption. However, designing an optical on-chip network requires addressing several challenges that have no equivalent in the electronic domain. In particular, photonic networks-on-chip suffer from considerable power loss, which affects the network scalability and impacts the performance by constraining the total number of wavelengths and hence the available bandwidth. In this paper, we propose an algorithm which automatically maps the IP cores onto a generic mesh-based photonic NoC architecture such that the worst-case power loss is minimized. As the main contribution, we first formulate the problem of power loss aware mapping and then we propose a genetic algorithm to solve it. Experimental results show that the power loss can be significantly reduced enabling much higher scalability of the on-chip photonic interconnect.