Logic synthesis based on decomposition for CPLDs

The paper presents a decomposition method dedicated for PAL based CPLDs. Non-standard usage of decomposition, which leads to the minimization of area in an implemented circuit and the reduction of used logic blocks in a programmable structure, is the aim of the proposed method. Each decomposition step (bound set selection, graph colouring, column pattern coding, etc.) is oriented for implementation in a PAL-based structure that is characterized by a PAL-based logic block. The proposed decomposition method is an extension of the classical approach, commonly thought to be adequately efficient. Experiments carried out on typical benchmarks show significant area reduction.