Superscalar architecture design for high performance DSP operations

This paper evaluates the possibility of using a general purpose superscalar architecture as the main computational engine for high performance DSP algorithms. Real-time sample rate conversion (SRC) in a software defined radio (SDR) has been taken as an example representing a class of computationally demanding DSP tasks. This scenario corresponds to digital filters operating at a high sampling rate in intermediate frequency (IF) stage of a multi-standard wireless transceiver. However, instead of a dedicated signal processing engine, a superscalar processor is designed for SRC implementation. An iterative, SimpleScalar based architectural modeling tool has been developed to analyze various parameters of superscalar processors. Both power and performance metrics have been taken under consideration to come up with an efficient design. It has been shown that the resulting superscalar architecture can provide a fully programmable solution capable of supporting future wireless communication standards in real-time. The design methodology explored in this work can be extended to obtain efficient processor architectures for a range of other applications.